Stability of p-GaN gate AlGaN/GaN HEMTs under static and dynamic drain stress

Abstract In this article, we report the investigation into the stability of p-GaN gate high electron mobility transistors (HEMTs) with an internal integrated gate circuit that led to the design of a capacitance-based circuit to address threshold voltage shifts (Δ V TH ). Pulse I–V measurement revealed a notable positive gate V TH shift of 0.7 V as the drain voltage increased from 0 to 650 V, highlighting the impact of drain bias on V TH instability. Through the investigation of drain bias-induced V TH instability and the behavior of carriers being transported within the gate region, it was found that the maximum Δ V TH is 0.4 V when a 200-V drain bias is applied; after stress removal, Δ V TH diminishes gradually due to the discharge of capacitance, and holes enter the p-GaN layer to mitigate the depletion of holes. The integration of passive components and p-GaN gate HEMT circuits is suggested to address V TH instability in enhancement-mode HEMT devices. The reliability of power devices is essential for their acceptance in emerging applications.