Optimal Defect Testing of Radiation-Tolerant SRAM for Spacecraft Avionics

Memory testing is an important, albeit time-intensive process when it comes to qualifying memory devices for use in electronic systems. With increasing device density, memory devices are prone to a multitude of failures, like Neighborhood Pattern Sensitive Faults (NPSF) that become more prominent due to coupling in bit arrays. Traditional memory tests and techniques like BIST that address all faults including NPSF require long test times, and often impact area and performance. In addition, memories used in spacecraft avionics are often augmented with radiation-tolerant features like Triple Modular Redundancy (TMR) and Error Correction Code (ECC) which may mask faults in individual memories, making testing all the more challenging. In this paper, we present an optimal test method developed for a highly configurable SRAM device which covers major faults like stuck-at, transition and coupling faults, along with a subset of NPSFs. This test method is developed with the knowledge of physical structure of the internal memory bit array, and adding configuration controls via device pins to isolate individual memory blocks within TMR structure. The proposed method allows for faster device qualification, achieving results with reduced test time and cost.