An 11-GHz Ultra-Fast Wideband FMCW Chirp Generator With 0.051% RMS Frequency Error Under 2.3-GHz Chirp Bandwidth and 2.3-GHz/ <i>μ</i> s Slope in 65-nm CMOS

An 11-GHz ultra-fast wideband frequency-modulated continuous-wave (FMCW) chirp generator with high linearity is presented for rapid walk-through imaging. To facilitate fast frequency modulation while reducing phase noise, a digital-to-time converter (DTC)-based sub-sampling phase-locked loop (SSPLL) with two-point modulation (TPM) technique is leveraged. Integrated with a ramp integrator, the proposed second-order curve-fitting (2nd-CF) digital predistortion (DPD) technique could remarkably mitigate the nonlinearities in the frequency modulation path while significantly reducing the hardware complexity. Meanwhile, a ramp tracker is parallelly utilized to initialize the lookup table (LUT) of DPD for a robust chirp linearity calibration. To reduce the idle time of the ultra-fast chirp without affecting its linearity, a modified DTC modulator is designed to achieve zero phase error at large frequency hopping moments. Furthermore, to achieve robust background calibrations in SSPLL, a voltage tracking loop (VTL) with a hold function is proposed to extract the phase-error sign and cooperate with the LUT to ensure an orderly convergence of the DPD. Fabricated in a 65-nm CMOS process, the FMCW chirp generator occupies a core area of 1.2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 50.8 mW. The measured maximum chirp bandwidth is 2.4 GHz, corresponding to 21.4% of the center frequency. A maximum chirp slope of 2.3 GHz/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s is achieved with 2.3-GHz chirp bandwidth, 1-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s chirp duration, and 50-ns idle time, and the largest measured rms frequency error is 1198 kHz for sawtooth and triangular chirps, corresponding to 0.052% of the chirp bandwidth.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-06-24
DOI
https://doi.org/10.1109/jssc.2025.3579724
Primary Topic
Acoustic Wave Resonator Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

An 11-GHz Ultra-Fast Wideband FMCW Chirp Generator With 0.051% RMS Frequency Error Under 2.3-GHz Chirp Bandwidth and 2.3-GHz/ μ s Slope in 65-nm CMOS

Xu Wu, Xujun Ma, Xiaohu You, Lianming Li et al.
IEEE Journal of Solid-State Circuits
Acoustic Wave Resonator Technologies
article

An 11-GHz Ultra-Fast Wideband FMCW Chirp Generator With 0.051% RMS Frequency Error Under 2.3-GHz Chirp Bandwidth and 2.3-GHz/ μ s Slope in 65-nm CMOS

Xu Wu, Xujun Ma, Xiaohu You, Lianming Li, Dongming Wang, Yupeng Fu, Xuan Wang
article en

Abstract

An 11-GHz ultra-fast wideband frequency-modulated continuous-wave (FMCW) chirp generator with high linearity is presented for rapid walk-through imaging. To facilitate fast frequency modulation while reducing phase noise, a digital-to-time converter (DTC)-based sub-sampling phase-locked loop (SSPLL) with two-point modulation (TPM) technique is leveraged. Integrated with a ramp integrator, the proposed second-order curve-fitting (2nd-CF) digital predistortion (DPD) technique could remarkably mitigate the nonlinearities in the frequency modulation path while significantly reducing the hardware complexity. Meanwhile, a ramp tracker is parallelly utilized to initialize the lookup table (LUT) of DPD for a robust chirp linearity calibration. To reduce the idle time of the ultra-fast chirp without affecting its linearity, a modified DTC modulator is designed to achieve zero phase error at large frequency hopping moments. Furthermore, to achieve robust background calibrations in SSPLL, a voltage tracking loop (VTL) with a hold function is proposed to extract the phase-error sign and cooperate with the LUT to ensure an orderly convergence of the DPD. Fabricated in a 65-nm CMOS process, the FMCW chirp generator occupies a core area of 1.2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 50.8 mW. The measured maximum chirp bandwidth is 2.4 GHz, corresponding to 21.4% of the center frequency. A maximum chirp slope of 2.3 GHz/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s is achieved with 2.3-GHz chirp bandwidth, 1-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s chirp duration, and 50-ns idle time, and the largest measured rms frequency error is 1198 kHz for sawtooth and triangular chirps, corresponding to 0.052% of the chirp bandwidth.

IEEE Journal of Solid-State CircuitsVol. 61(2)
Southeast University (CN)
National Key Research and Development Program of China
Affordable and clean energy
Openalex Percentile: Top 86%
Acoustic Wave Resonator Technologies
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