A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues

This article presents a hybrid voltage-time domain pipelined analog-to-digital converter (ADC). The proposed ADC employs a voltage-domain SAR quantizer for the coarse stage, while a time-domain quantizer is used for the fine stage. Ahybrid-domain dual-residue method is proposed to generate reference-embedded time-domain residues. It ensures full-scale matching between the converted time-domain residue and the time-domain reference of the fine stage. For the fine stage sub-quantizer, an interpolating time-to-digital converter (TDC) suited for dual-residue quantization is employed without using an external time-domain reference. A prototype ADC, implemented in a 40-nm CMOS process, occupies 0.034 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Operating at a sampling rate of 150 MS/s, the ADC achieves an SNDR of 61.1 dB and an SFDR of 75.5 dB at a Nyquist input, while consuming 2.54 mW, resulting in a Walden figure-of-merit (FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub>) of 18.3 fJ/conv.-step.