Implementation of 8-bit Digital Comparator with Low Power and Low Area for High-Speed Applications

This research introduces a highly efficient digital comparator designed to handle 8-bit comparisons, with a primary focus on achieving minimal area usage, maximum speed, and low power consumption. The Comparative Analysis Block (CAB) as well as the Termination Block (TB) are the two key modules which make the comparator. The CAB is organized and uses periodic logic gates to build a parallel prefix tree. The consistency of the implementation is maintained irrespective of the bit-width of the input operands. Concurrently, the TB verifies the comparative outcomes obtained by the CAB. Through extensive spectre simulations conducted using 0.09 μm CMOS technology operating at a clock frequency of 1 GHz, significant advantages such as minimal input-output delay and low power dissipation are demonstrated. Notably, this comparator outperforms existing designs utilizing 90 nm CMOS technology for conducting 8-bit comparisons.