Enhancing FPGA Security: An AI-Driven Approach to Root of Trust Architecture
The security of Field-Programmable Gate Arrays (FPGAs) is a growing concern due to the increasing complexity of cyber threats. Traditional Root of Trust (RoT) architectures in FPGA-based systems rely on static security mechanisms that struggle to adapt to emerging attack vectors. This paper presents an AI-driven FPGA- based RoT framework that enhances security by integrating machine learning (ML) and deep learning (DL) for real-time threat detection, adaptive security policy enforcement, and blockchain-assisted firmware verification. The proposed architecture consists of three key components: an AI-Powered Threat Detection Module (AI-TDM) for anomaly detection, an Adaptive Security Policy Engine (ASPE) for dynamic policy adjustments, and a Blockchain-Assisted Firmware Verification (BFV) mechanism to prevent unauthorized modifications. Through comparative analysis, the proposed framework demonstrates improved security robustness, reduced response time, and enhanced adaptability compared to conventional RoT approaches. By leveraging AI and blockchain technologies, this solution addresses existing security gaps in FPGA-based architectures, paving the way for resilient and intelligent hardware security systems.
Authors
- Isha Malhotra (ORCID: https://orcid.org/0000-0003-3027-6158)
- Yogendra Kumar Sharma (ORCID: https://orcid.org/0000-0002-6678-8027)
- Pratham Kaushik (ORCID: https://orcid.org/0009-0006-3895-3626)
Publication Details
- Published
- 2025-03-06
- DOI
- https://doi.org/10.1109/ispcc66872.2025.11039435
- Primary Topic
- Physical Unclonable Functions (PUFs) and Hardware Security
- Type
- article
- Field-Weighted Citation Impact
- 0.00