Neural Network-Enhanced Fault-Tolerant SRAM with Adaptive Error-Correcting Code

Fault tolerance in digital circuits is crucial for ensuring reliable operation in critical applications. This research focuses on enhancing the fault tolerance of an 8-bit Static Random Access Memory (SRAM) system by integrating traditional error-correcting techniques with neural network-based approaches. An 8-bit fault-tolerant SRAM circuit was designed and simulated using Logisim, incorporating Hamming Code (12,8) for single-bit error detection and correction. The system detects errors using parity bits and corrects them by decoding a 4-bit syndrome vector to identify and flip the erroneous bit. Additionally, a neural network model was trained on error datasets to predict corrected outputs, providing an intelligent alternative for fault mitigation, especially in scenarios where traditional methods may be insufficient. To enhance precision, the neural network was optimized by refining its architecture, adjusting hyperparameters, and increasing the training dataset size. The neural network’s performance was evaluated using a confusion matrix and ROC curve, demonstrating its effectiveness in improving error detection and correction accuracy. The proposed system was further implemented in Xilinx Vivado, where power consumption analysis revealed a total power utilization of 2W, with 1.972W dynamic power and 0.028W static power. The study highlights the potential of combining classical and AI-driven error correction techniques to enhance fault tolerance in SRAM-based systems. These advancements have significant applications in embedded systems, aerospace, healthcare devices, and other domains requiring robust digital memory architectures.