Design and Analysis of Low Power Level Shifters in CMOS Technology

The multi-supply voltage (MSV) design technique is one of the main technologies in modern systems on chips (SoCs) and brings an effective balance between energy efficiency and performance frequency. This paper presents a level shifter design that has the ability to efficiently interface different voltage domains with low power consumption and fast operation. By adopting the use of sub-threshold CMOS technology, the proposed system provides robust voltage shifting across varied voltage domains. The design is implemented using 45nm, 90nm, and 180nm for transient CMOS technology nodes, and the simulation is carried out by Cadence Virtuoso. The performance metrics under investigation include delay, average power, power- delay product (PDP), and energy delay product (EDP), which offer a complete analysis of the system’s efficiency in different technology nodes. Simulation results show how scaling technology impacts the performance of the level shifter. The Power efficiency increases and delay is reduced since the capacitance is lower and the switching speed is higher To summarize, this work is useful to develop better level shifter configurations to achieve greater power efficiency while achieving high working frequency.