2T1M and Complementary 3T2M Type-XY SOT-MRAM With High Performance and High Density

Type-XY SOT-MRAM is promising to achieve smaller footprint compared to the type-Y cells, and to circumvent the non-deterministic characteristic suffered by the type-X switching. This work verifies the high performance of type-XY switching in a 2-transistor-1-memory (2T1M) array, showing the capability of low write-error-rate (<0.1%) and low switching current density under high writing speed (~69.6 MA/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>@1ns). Combining these advantages with the polarity-controllable characteristics, a novel complementary type-XY device is demonstrated in 3-transistor-2-memory (3T2M) configuration by sharing the SOT line. This 3T2M device is capable of fast and efficient one-pulse complementary switching (1V@10ns), high endurance (8×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup>cycles@±0.8V/100ns) with low write error rate (<0.1%@1V/500ns). In the advanced CMOS technology nodes, using type-XY cells is projected to outperform the traditional solution using type-Y cells: 0.61× cell size with 0.41× write power in traditional 2T1M, 0.67× cell size with 0.10× operation power in 3T2M for complementary write function. Considering the sharable processes between 2T1M and 3T2M, using type-XY cells can be a fabrication-friendly solution to facilitate the integration of multifunctional memories in the advanced chips.