Optimized Design of Clock-Gated D Flip-Flop using Transmission Gate

Modern digital applications will call for very fast and optimum devices because they are associated with minimal delay and power. Through a transmission gate, the proposed design employs a low-power clock pulsed data flip-flop (D flip-flop). This study proposes to use the clock gating technique to design a low-power pulsed D flip-flop. By reducing transistor switching, the gated clock reduces the circuit's dynamic power usage. One of the methods of applying clock gating is to disrupt the circuit’s clock input using an OR gate in relation to the signal Enable. This method makes the clock idle to reduce power consumption when the output is at a particular steady state. This research therefore puts forth a concept of a clock-pulsed low power D Flip Flop (DFF) structural design based on the use of transmission gates to enhance the power efficiency of digital circuits. The proposed DFF is intended for constructing a 4-bit serial in parallel-out shift register to show the efficient performance of low power applications. The cadence tool with 90nm technology is also used to simulate all the designs and what is observed is that the tool provides better power, number of transistors, and delay efficiency.