A 7-Bit 1.41-GS/s 2-Bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator

A compact high-speed 2-bit/cycle SAR ADC with precharge-advancing operation is proposed. By leveraging an advanced clocking scheme, the reference DACs are fully precharged within the sampling phase, thereby eliminating additional timing overhead. A three-stage comparator with a fast-discharge technique further improves conversion speed. To enhance robustness, a redundancy scheme is introduced to correct errors during operation. Fabricated in 22-nm CMOS, the 7-bit prototype ADC operates at a 1.41 GS/s sampling rate under a 1V supply, achieving an SNDR of 39.6 dB at Nyquist frequency and a Walden figure-of-merit (FoMW) of 23.5 fJ/conversion step, with a total power consumption of 2.59mW. The proposed architecture achieves the highest conversion speed among state-of-the-art single-channel 6–X;8-bit SAR ADCs.