Theoretical and hardware-level precising in MASH 1-1-1 modulators with eliminable dither

Abstract This manuscript explores Digital Delta-Sigma Modulators, commenting on the limitations of the eliminable dither in a Multi-stAge-noise-SHaping solution. The mathematical analysis in this work provides evidence, through a quantitative study, of the periodicity for eliminable dither and the Song and Park Multi-stAge-noise-SHaping modulators. The work presents the necessary considerations for the unexplored physical and digital synthesis implementation, commenting on the hardware limitations of the eliminable dither solution. The manuscript proposes a new dithering scheme with a feasible digital synthesis in a standard cell CMOS integrated circuit design. The solution uses an XOR-based signal feedback, extending the modulator’s periodicity with fourteen percent of additional hardware, representing a low-cost solution compared with similar systems.

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Publication Details

Journal
Analog Integrated Circuits and Signal Processing
Published
2025-06-24
DOI
https://doi.org/10.1007/s10470-025-02445-6
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

Theoretical and hardware-level precising in MASH 1-1-1 modulators with eliminable dither

Rosalba Perdomo-Cosme, Víctor R. González-Díaz, Gisela De La Fuente-Cortes, Maria M. Perez-Torres
Analog Integrated Circuits and Signal Processing
Advancements in PLL and VCO Technologies
article

Theoretical and hardware-level precising in MASH 1-1-1 modulators with eliminable dither

Rosalba Perdomo-Cosme, Víctor R. González-Díaz, Gisela De La Fuente-Cortes, Maria M. Perez-Torres
article en

Abstract

Abstract This manuscript explores Digital Delta-Sigma Modulators, commenting on the limitations of the eliminable dither in a Multi-stAge-noise-SHaping solution. The mathematical analysis in this work provides evidence, through a quantitative study, of the periodicity for eliminable dither and the Song and Park Multi-stAge-noise-SHaping modulators. The work presents the necessary considerations for the unexplored physical and digital synthesis implementation, commenting on the hardware limitations of the eliminable dither solution. The manuscript proposes a new dithering scheme with a feasible digital synthesis in a standard cell CMOS integrated circuit design. The solution uses an XOR-based signal feedback, extending the modulator’s periodicity with fourteen percent of additional hardware, representing a low-cost solution compared with similar systems.

Analog Integrated Circuits and Signal ProcessingVol. 124(2)
Benemérita Universidad Autónoma de Puebla (MX)
Consejo Nacional de Ciencia y Tecnología
Openalex Percentile: Top 87%
Advancements in PLL and VCO Technologies
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Theoretical and hardware-level precising in MASH 1-1-1 modulators with eliminable dither — Rosalba Perdomo-Cosme, Víctor R. González-Díaz, et al. · Analog Integrated Circuits and Signal Processing (2025) | TGRS Research Map | TGRS