Computing in Memory Optimized Based on Multi-Level Carry Lookahead Adder

This article aims to optimize the operating speed of an SRAM-based computing-in-memory circuit by designing speed-optimized local computation units (LCUs), adder tree modules (ADDERTREE), and shift-accumulate modules. It also proposes a multi-level carry lookahead adder for area optimization of the aforementioned modules and the entire circuit. The LCUs are composed of 6T SRAM and 1T computational units, the adder tree module is fully replaced by a multi-level carry lookahead adder, and the shift-accumulate module is optimized using a combination of multi-level carry lookahead and ripple carry. This approach reduces the number of cycles for data accumulation calculations, thereby achieving the goal of optimizing the computing-in-memory speed.