Performance Improvement of 9T SRAM Cell by Efficient Memory Design

This paper presents the design and simulation of a 9T SRAM cell to achieve significant performance improvements. The proposed design focuses on reducing power consumption, which is crucial for extending the battery life of portable and energy-constrained devices. The paper explores methods for improving performance and addressing critical challenges in modern memory technology. The simulation results in 90nm CMOS technology at 1.2 V demonstrate a 31% reduction in total power consumption and 41% reduction in leakage power that minimize energy losses and ensure efficient operation.