Design of Software Security Architecture for FPGA Electronic Security Systems

To improve the security of the electronic security system, an FPGA-based software architecture design for the electronic security system is proposed. Firstly, the overall redundancy architecture of the system is designed, and 2003D redundancy architecture is proposed. To ensure the security and consistency of data, a built-in voter is intended for the FPGA information transmission process. Then we analyze the failure rate concerning the IEC 62061 standard and design a redundant voting architecture for FPGA by combining the 2003D redundant architecture and the built-in voter. The program design of the FPGA redundant voting architecture needs to make master-slave decisions for multiple channels to avoid data conflicts. Logic simulation of the security system using FPGA shows that this security architecture can better ensure the security of data transmission, which has certain practical significance and application value.