Hybridized Efficiency: A Combined Approach of Parallel Prefix and Hybrid Adders for High-Performance Arithmetic Circuit

The aim of this project is to explore the benefits of combining Brent Kung Adder (BKA) and Cary Select Adder (CSA) architectures to develop a new efficient adder. BKA is known for its low propagation delay and regularity, making it more efficient for parallel computing. On the other hand, CSA reduces the maximum delay by selecting the receiver from two parallel connectors based on the transmit signal. Combining these two architectures, we created a design that takes advantage of the strengths of both approaches. BKA’s standard design ensures scalability and ease of use, while CSA’s transmission selection mechanism helps significantly reduce path delays. This combination can significantly improve speed performance compared to traditional ones. The project involves the design and methodology of an integrated BKA-CSA system using a hardware description language such as Verilog. Performance metrics such as power consumption, latency and area consumption are evaluated and compared to existing redundancy plans. The ultimate aim is to illustrate the process of the proposed architecture in fast mathematical applications that can be applied, for example, in Digital Signal Processing (DSP) and efficient computing.