Design of the Receiver Circuit for RS485 Interface Chips

This paper designs a receiver circuit for an RS485 interface chip. To achieve a wide common-mode input voltage range of -7 V to 12 V, the receiver input circuit adopts a structure combining a voltage divider resistor network and a level shift circuit to compress the input signal to 0 V to 5 V. For the receiver comparator, an offset current is introduced to make the receiver comparator have a hysteresis range and full fault protection function. The circuit design and simulation are completed based on the 0.18 μm 30 V BCD process. The simulation results show that within the common-mode voltage range of -7 V to 12 V, the positive and negative threshold voltages of the receiver are -60 mV and -190 mV respectively, and the hysteresis voltage is 130 mV.