Delay Models for RLCG Global Interconnect Based on Single and Two Pole Analysis

With the time of development in VLSI design, interconnection delay plays a dominating role as compare to the gate delay. In transmission line the signal delay analysis represented with a LC interconnects [5] which are lossless and low frequency interconnection, but for the high frequency interconnection, we have to model the distributed RLCG line. We derive the new expression for the first and second order of transfer function of interconnects by using single and two pole analysis methodology. This article also represents the suitable VLSI design with its advantages in accuracy, simulation results and minimum time required for significant operation. This analysis, introduce faster techniques such as the single and two pole [10] approaches to calculate the response of ramp input of RLCG interconnects.