Design of High-Speed and Low-Power Sense-Amplifier-Based Flip-Flop : Low redundancy flip-flop design

The increasing power consumption of integrated circuits has become a significant concern, making low-power design a crucial area of research. This paper proposes a novel sense-amplifier-based flip-flop design using bridge control. The proposed YC SAFF employs a Y-type circuit bridge to manage the pre-charge node and triangular region of traditional sensitive flip-flops, thereby enhancing performance and reducing power consumption. Detailed PSPICE simulation results indicate that the YC SAFF reduces power consumption 16.25% and the power delay product 27.6% under 25% switching activity conditions compared to existing SAFFs. The proposed design exhibits favorable power consumption and delay characteristics. Simulations of half and quarter dividers using the proposed flip-flop confirm its correct functionality and robustness.