Novel FPGA based Systolic Array Design for Dynamic Workflows

Convolutional neural network based object detection is an inevitable part of advanced driver assistance systems which has high accuracy and low latency requirements. Considering the high computational complexity of CNNs, it is essential to have customized hardwares to boost their performance. In this regard it is essential to implement an optimized CNN algorithm on FPGA. The high energy efficiency, parallel computing capabilities and reconfigurabilty of FPGAs makes it suitable for hardware acceleration of CNNs. In this work a modified dynamic systolic array based CNN accelerator is implemented targeting PYNQ Z2 FPGA board where the most suitable architecture among the three typical systolic array architectures is selected based on the workload. Here, the processing element of systolic array is designed using brain floating point 16 bit format to accommodate better data range as compared to floating point 16 bit format. The results of the model with respect to floating point operations are analysed.