Reconfigured System on Chip (SoC) design for Gradient Descent Acceleration via Hardware-Software Co-design

Machine Learning (ML) algorithms need an extensive computational power with energy efficient platform to implement the algorithms. Field Programmable Gate Array (FPGA) devices are being used in much well-known industry cloud applications as it can offer low power consumption and high throughput. Due to both dynamic and energy efficient nature of the high-speed performance making FPGA suitable for handling work load like Machine Learning Algorithms. This paper discusses about the Gradient Descent Algorithms (GDA) and its SoC implementation on FPGA (Basys-3) by taking the advantage of the parallelism that dynamically changes the run time of the algorithm. The implemented SoC incorporates VHDL (Very High Speed Integrated Circuit Hardware Description Language) in its design AXI4 stream interface thus making it possible for smooth connection in the chip. The overall design partitioned into fixed hardware (designed using the Programmable Logic part of the FPGA) and flexible software (designed using the 32-bitmicroblaze IP). Gradient Descent Algorithm is implemented on reconfigurable and tunable PL part, Microblaze acts as the Host to the overall design and AXI4 creates a smooth interface between Microblaze-IP and GDS-IP. The results of the analysis shows that a 9X speed-up is achieved when the hardware software co-design is implemented on Artix XC7A35T-1CPG236C FPGA, as opposed to simple software based on 32-bit Microblaze based design.