Enhancement of AES Security On FPGA: Mitigating Side Channel Attacks

This work proposes a hardware-augmented variant of the Advanced Encryption Standard (AES) to mitigate sidechannel attack (SCA) vulnerabilities. A suite of countermeasures, including noise injection, dummy operations, and current smoothing—aimed at normalising power and electromagnetic emissions, has been applied and evaluated. The augmented AES architecture is synthesised and evaluated on a field-programmable gate array (FPGA) platform using Vivado, demonstrating functional correctness and enhanced resistance to physical attacks with little resource overhead. This approach indicates the efficacy of integrating lightweight defences in cryptographic hardware, offering a fair trade-off between security and performance in practical implementations.