Performance Analysis of High Speed Low Power BCD Adder using CMOS and Dynamic logic

Background: In the field of high-speed digital circuits, the efficiency of Binary Coded Decimal (BCD) adders consists of significant importance in optimizing the speed of arithmetic operations in computing systems. BCD arithmetic is crucial in scientific and financial computing systems that require decimal accuracy. Objectives: This study examines the performance of BCD adders as designed using two different logic families, Complementary Metal Oxide Semiconductor (CMOS) and dynamic logic. CMOS logic which is meant to have low static power dissipation and dynamic logic which is meant to have high-speed switching capabilities and reduced transistor count. Methods: A new dynamic logic realization of a high-speed BCD adder improved from the previously introduced CMOS-based BCD adder is presented in this work. Dynamic logic design keeps the same pull-down network as the equivalent CMOS but with a precharge PMOS and an evaluate NMOS transistor. This design is implemented under 45nm technology and is optimized for a single digit BCD adder. Schematics are made using DSCH, and Verilog files were developed which are simulated using MICROWIND 3.9. The delay and power dissipation values are obtained with an operating voltage of 1V, and a parametric analysis was conducted comparing delay, and power dissipation for varied temperatures in the range (-40°C to 120°C). Findings: The findings depict enhanced performance of dynamic logic implementation compared to static CMOS implementations with reduced power dissipation and increased switching speed due to the inherent benefits of dynamic logic. Novelty: For comparison purpose this work also implements two different adders along with the static CMOS logic implemented adder which are already present in literature. The final results depict that dynamic logic implemented adder outperforms all the three adders with a power delay product (PDP) of 14.75 fJ when compared to 72.07 fJ, 80.48 fJ, and 50.92 fJ PDP of other works. Keywords: BCD adder, CMOS logic, Dynamic logic, Pull down network, Precharge, Evaluate, Parametric analysis, Delay, Power dissipation, Power delay product (PDP)