Design and Performance Optimization of a Risc-V Processor with Five-Stage Pipeline

Research on RISC-V-based microprocessors has advanced rapidly in recent years in China, though performance evaluation studies primarily focus on 2-3-stage pipeline processors. To address this limitation, this paper presents the design of a fivestage pipelined microprocessor based on the open-source RISC-V instruction set architecture. To mitigate pipeline hazards, the processor incorporates data forwarding and branch prediction techniques. The design is implemented in Verilog, and its logical functionality is verified through simulation using custom-written assembly test programs. After applying timing and physical constraints in Vivado synthesis tools, logic synthesis is performed, and hardware resource utilization is analyzed. Experimental results demonstrate that the proposed processor achieves correct logical functionality with low hardware overhead, making it suitable for cost-constrained embedded applications.