Research on a Method for Evaluating SEL and SEU in a Time-Interleaved High-Speed ADC
Time-interleaved high-speed analog-to-digital converter (ADC) have emerged as pivotal components in high-speed systems such as phased array radars and satellites in recent years. However, in aerospace environments, they are susceptible to heavy ions, which can lead to the failure of related functions. This paper proposes an evaluation method for single-event latch-up (SEL) and single-event upset (SEU) in high-speed ADC by analyzing the internal structure of time-interleaved ADC and studying the mechanism of single-event effects. A test and verification system for high-speed ADC single-event effects is implemented using methods such as the K-value method, frequency difference method, and WRMA. Corresponding heavy-ion experiments were conducted at the Harbin Space Environment Simulation Research Institute (SESRI) and the tandem electrostatic accelerator (H-13) of the China Institute of Atomic Energy, successfully capturing instances of SEL and SEU. Subsequent laser simulation experiments were performed to analyze and pinpoint weaknesses in the device layout reinforcement, providing significant guidance for future design reinforcement efforts.
Authors
- Yifeng Wei (ORCID: https://orcid.org/0000-0002-0348-7999)
- Yu Zhou (ORCID: https://orcid.org/0000-0002-2102-9377)
- Disong Fu (ORCID: https://orcid.org/0000-0003-1599-7192)
- Xianchao Wen
- Tianqi Wang (ORCID: https://orcid.org/0000-0002-7503-602X)
- Wei Jiang (ORCID: https://orcid.org/0000-0002-6742-5199)
Institutions
- Chongqing University of Technology (CN)
Publication Details
- Published
- 2025-04-16
- DOI
- https://doi.org/10.1109/icreed65908.2025.11036193
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00