Recent Challenges in the Fabrication of Vertical Silicon Nanowire Transistors

Vertical silicon nanowire transistors are among the most promising device concepts for future low-power electronics due to their gate-all-around nature as well as their 3D stacking potential. In this work we review the current status of transistor fabrication on vertical silicon nanostructures and identify the most important challenges for successful process integration. Channel patterning, source/drain contact formation, gate-deposition and spacer engineering are identified as key steps independent on the actual process integration sequence. We conclude the paper with two emerging device examples and discuss the influence of the processing challenges on the transistor design.

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Publication Details

Journal
IEEE Transactions on Nanotechnology
Published
2025-01-01
DOI
https://doi.org/10.1109/tnano.2025.3582023
Citations
2
Primary Topic
Nanowire Synthesis and Applications
Type
article
Field-Weighted Citation Impact
1.35
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article

Recent Challenges in the Fabrication of Vertical Silicon Nanowire Transistors

Jens Trommer, Thomas Mikolajick, Sylvain Pelloquin, Guilhem Larrieu et al.
2 citations
IEEE Transactions on Nanotechnology
Nanowire Synthesis and Applications
1.35
article

Recent Challenges in the Fabrication of Vertical Silicon Nanowire Transistors

Jens Trommer, Thomas Mikolajick, Sylvain Pelloquin, Guilhem Larrieu, Çiğdem Çakırlar, Giulio Galderisi, Bruno Neckel Wesling, Κωνσταντίνος Μουστάκας, C. J. Beyer, Jonas Müller, Cristell Maneux
article en
2 citations

Abstract

Vertical silicon nanowire transistors are among the most promising device concepts for future low-power electronics due to their gate-all-around nature as well as their 3D stacking potential. In this work we review the current status of transistor fabrication on vertical silicon nanostructures and identify the most important challenges for successful process integration. Channel patterning, source/drain contact formation, gate-deposition and spacer engineering are identified as key steps independent on the actual process integration sequence. We conclude the paper with two emerging device examples and discuss the influence of the processing challenges on the transistor design.

IEEE Transactions on NanotechnologyVol. 24
Centre National de la Recherche Scientifique (FR), Université de Bordeaux (FR), Université Fédérale de Toulouse Midi-Pyrénées (FR), Laboratoire d'Analyse et d'Architecture des Systèmes (FR), NaMLab (Germany) (DE), Laboratoire de l'Intégration du Matériau au Système (FR), Institut Polytechnique de Bordeaux (FR)
Openalex Percentile: Top 19%
Nanowire Synthesis and Applications
1.35
DOIOpen Access PDFOpenAlex
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Recent Challenges in the Fabrication of Vertical Silicon Nanowire Transistors — Jens Trommer, Thomas Mikolajick, et al. · IEEE Transactions on Nanotechnology (2025) | TGRS Research Map | TGRS