Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies

• This work primarily consisted of the following components: Using ten transistors and multiplexer choice logic, we first create an improved full adder (IFA). Changes to the IFA's carry input and carry out features resulted in the creation of carry-input selective full adders (CISFA) and carry output predicted full adders (COPFA). In addition, we created a 4-bit delay-controllable adder and subtractor using IFA, CISFA, and COPFA components. • We constructed the delay-controllable subtractor using the two complementation addition characteristics as its essential components. The 4-bit delay-controllable adder and subtractor modules are expanded to include reconfigurable features. This makes an N-bit delayed-controlled reconfigurable hybrid adder, subtractor, and adder-subtractor possible. Furthermore, • we have created a 4-bit delay-controllable multiplier using delay-controllable adder components and expanded it with an N-bit delay-controlled reconfiguration array. A reconfigurable ALU with delay control had been developed with delay-controllable adders, multipliers, and mathematical operations employing FinFET and CNTFET technology. Simulation results demonstrate that the suggested models outperform traditional adder circuits and subtractors in terms of area, power, as well as latency. The Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays. This investigation intends to develop a delay-controlled reconfigurable ALU employing advancements in FinFET (Fin Field Effect Transistor) Carbon Nano Tube Field Effect Transistor and (CNTFET) technology. The first development is the integration of Carry Output Predicted Adders (COPA) along with Carry Input Selective Adders (CISA) employing multiplexing selection circuitry, allowing the development of adders and subtractors with controllable delay. The Delay Controllable Reconfiguration ALU may be built by integrating arithmetic and logical functions. Nanotechnology-based techniques exceed traditional adders and subtractors regarding power efficiency and latency. The outcome results have been obtained with Cadence Virtuoso utilizing 18nm finFET technological advances, having supply voltages between 0.8V and 1V and temperatures between -25°C and 50°C. Simulation findings indicate that the suggested 4-bit ALU has remarkable stability. The proposed CNTFET 4-bit Arithmetic Logical Unit (ALU) exhibits a 30% decrease in power consumption and a 40% decrease in delay time relative to existing 4-bit ALUs.