Comparative Analysis of Error Tolerance and Hardware Efficiency in Stochastic Computing-based Digital Filters

The demand for cost-effective digital filters in near-sensor computing has aroused interest in stochastic computing (SC) as a promising alternative to traditional binary approaches. This study investigates in detail the error tolerance and hardware cost of SC-based digital filters of both the finite and infinite impulse response (FIR and IIR) types, focusing on their stochastic number generation and addition methods. We demonstrate that SC filters need only about half the area and power of binary designs under error-free conditions, though with a slight reduction of accuracy. Furthermore, these filters exhibit strong error resilience, with only 4X and 6X performance degradation under a 3% bit-flip rate, significantly outperforming their binary (non-SC) counterparts. We also compare the error tolerance of SC filters against binary filters equipped with triple modular redundancy (TMR). Our results indicate that for FIR filters, SC-based designs remain far more error-tolerant than binary FIR filters with TMR. However, in the IIR case, the binary designs with TMR outperform SC-based IIR filters at higher error rates. These findings highlight the possible trade-offs between SC and binary implementations, with SC offering more robust error tolerance, significant area and power savings and manageable accuracy trade-offs in most cases. This work also underscores SC’s potential as an efficient, resilient approach for low-cost digital filtering in edge devices and near-sensor computing applications.