Design and Analysis of High Efficiency Operational Transconductance Amplifier

High efficiency operational transconductance amplifier is an important analog circuit designed to optimize the balance between power consumption and performance. This amplifier is suitable for mobile devices, sensor interfaces, and other low-power applications due to its high gain and low power consumption characteristics. This article provides a design for implementing a high-efficiency operational transconductance amplifier, which achieves higher gain and bandwidth on the basis of traditional common source and common gate. A recycling folded cascode amplifier with bias circuit was designed using Cadence 0.18 m CMOS technology. The power consumption and load capacitance of the two circuits were the same and the various parameters of the two circuits were simulated and verified. Sacrificing some phase margin under small signal conditions increased the gain by 6dB, bandwidth by 1.89 times, and the speed of the operational amplifier was accelerated; The slew rate under high signal is 1.5 times faster than before, and the setup time is shorter. The CMRR and PSRR have both been improved.