Standardized RISC-V Near-Memory Processing: A Scalable Approach to Data-Intensive Workloads

Modern computing faces a significant memory wall problem due to heavy data transfers between memory subsystems and processors, causing bottlenecks and excessive power consumption. Processing-In-Memory (PIM) architectures mitigate these issues by bringing compute units and memory closer. This approach aims to offload select compute-intensive tasks from the main processor to a near- or in-memory processor, thereby lowering the data movement overhead and enhancing performance and energy efficiency. The proposed RISC-V-based near-memory processor (NMP) is designed to operate with the main processor in parallel in a system architecture that features distinct memory controllers and a standardized Avalon-Mm interface, which allows functionality extensions like adding watchdogs for enhanced reliability, Application-Specific Instruction Set Processors (ASIPs) for better power and performance profiles, or anything similar. The implementation was evaluated on a Cyclone V FPGA. The design employs one fully featured main processor for heavy tasks and a streamlined NMP for simpler, data-intensive operations. Experimental results demonstrate that total job time can be reduced by a range of 32% to 42% and energy consumption improved by a range of 16% to 21% under varying bus contention scenarios compared to a single-processor system. The system achieves scalable and easy-to-adopt hardware/software integration. These findings indicate that a standardized NMP-based architecture offers a scalable and energy-efficient solution to alleviate the memory wall problem across data-intensive workloads.