Efficient Mixed-Radix FFT Architecture for High-Performance Communication Systems

Mixed-radix Fast Fourier Transform (FFT) algorithms play a crucial role in advanced communication systems such as 5G. However, in the conventional decimation-in-time (DIT) FFT algorithm, the input time-domain sequence and intermediate-stage data are not arranged in a natural order, creating a mismatch between the processing element (PE) computation speed and memory bandwidth. Additionally, multiple redundant interstage twiddle factor (TF) generation units operate in parallel to supply TFs, leading to inefficiencies in both computational and storage resources. This article introduces a flexible and reconfigurable architecture that utilizes a mixed-radix FFT approach, supporting FFT sizes from 8 to 4096 points. To enhance hardware efficiency, a CGR-based multi-parallel changeable-radix butterfly unit (BU) is incorporated. Moreover, a conflict-free memory access mechanism, featuring an optimized address generation scheme, is designed around the PE array. A TF sharing and compression technique is also employed to reduce both the area and latency of the TF generation units.