Design and Optimization of a Low-Power Phase-Locked Loop Using 18nm FinFET Technology for High-Performance Applications

The Modern-day electronic systems rely on Phase-Locked Loops (PLLs) for wireless communication together with high-speed data processing and RADAR applications. CMOS-based traditional PLL designs encounter two main drawbacks that result in poor efficiency during low- power operations because of excessive power usage and leakage current flow. A new PLL design using 18nm FinFET technology introduces solutions for resolving existing restrictions. FinFET transistors provide better electrostatic control combined with reduced leakage currents and improved performance when operating at low voltages so they work well in power-efficient circuits. The proposed design of PLL includes fundamental modules which consist of Phase Frequency Detector (PFD), charge pump, Voltage-Controlled Oscillator (VCO), and frequency divider. All components undergo precise optimization procedures to achieve both reduced static power consumption and dynamic power as well as frequency synchronization precision. A Simulations platform using Cadence Virtuoso evaluates precise power efficiency and stability performance of the designed system. Reduction of supply voltage from 1V to 0.6V in the FinFET-based PLL delivers 22.28 μW operational power while achieving a 56.14% lower consumption than conventional 45nm CMOS-based PLLs operating at 50.8 μW. The FinFET-based PLL design produces simulation data which shows quick locking phase noise stability alongside energy-saving capabilities that qualify it as a strong option for future electronic applications. The research findings demonstrate that FinFET implementation in PLL structures increases energy efficiency to meet the market needs for low- power high-performance integrated circuits.