Memory and Power Efficient Multiplier Design using I-ANT Architecture

The I-ANT (Interleaved Approximation Neural Transformation) Multiplier Architecture addresses the challenges of memory and power inefficiency in traditional multiplier designs, making it suitable for modern low-power, high-speed applications. The proposed architecture integrates interleaved approximation techniques and neural-inspired transformations, achieving significant improvements in computational efficiency while maintaining acceptable accuracy levels. Results demonstrate that the I-ANT multiplier reduces memory usage by up to 34.37% for 32-bit operands compared to Booth multipliers. Power consumption is lowered by 37.87%, and latency is improved by 26.3% for 64-bit operations, demonstrating its superior performance. The trade-off between accuracy and resource efficiency is also evaluated, with an approximation factor (A_f) ranging from 0.0 to 1.0. At A_f =0.4, the I-ANT multiplier achieves 95% accuracy, alongside 33% memory reduction and 30% power savings, making it highly adaptable to diverse application requirements. Additionally, the Power-Delay Product (PDP) is reduced by up to 56.34% for larger operand sizes, underscoring its energy efficiency. The architecture's scalability and make it an excellent choice for energy-sensitive systems like IoT devices, AI accelerators, and embedded applications. This study highlights the potential of I-ANT to revolutionize multiplier designs by balancing power, memory, and accuracy, providing an innovative solution for computationally intensive tasks.