Horizon Detection Hardware Accelerator for FPGA Based Space Computers

As humanity probes deeper into the solar system and becomes increasingly dependent on satellite technology for everyday life, the need for more powerful, resilient, and cost-effective space computing systems is increasing. This paper presents an image processing hardware accelerator design implemented on a Xilinx Artix-7 200T FPGA and integrated into a RISC-V soft processor system housed on the same FPGA. The system described performs horizon detection and computes orientation information from live, streaming camera data received from an on-board camera. It then displays the live data along with horizon and orientation correction overlays on an onboard liquid crystal display. Design solutions along with verification test setups and results are discussed. Testing results showed that the system was able to display 320 x 240-pixel live video at 30 frame per second with horizon and orientation overlay calculations being refreshed at 15 Hz using a processor running at 32 MHz. The design demonstrated the performance enhancing capabilities that custom hardware accelerator blocks can have on small satellite computers without requiring the use of additional resources.