Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency
This paper proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high peak efficiency of 95.5%.
Authors
- Minxiang Gong (ORCID: https://orcid.org/0000-0002-5426-7697)
- Yichen Xu (ORCID: https://orcid.org/0009-0001-0294-908X)
- Mingoo Seok
- Xin Zhang (ORCID: https://orcid.org/0000-0002-0579-2268)
- Rongqiao Wan (ORCID: https://orcid.org/0000-0002-1052-5199)
- Ram Krishnamurthy (ORCID: https://orcid.org/0000-0002-2428-7099)
- Suhwan Kim (ORCID: https://orcid.org/0000-0001-9107-2963)
- Zhaoqing Wang (ORCID: https://orcid.org/0000-0002-5548-3965)
Institutions
- Intel (United States) (US)
- Columbia University (US)
Publication Details
- Journal
- IEEE Solid-State Circuits Letters
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/lssc.2025.3581844
- Primary Topic
- Advanced DC-DC Converters
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Semiconductor Research Corporation