ACRIN: Asymmetric Compression‐Recovery Interconnection Network for Inter‐Chip Sparsity Architecture

ABSTRACT Chiplet architecture and sparsity are two pivotal technologies driving the advancement of AI chip development, particularly for AI large models. In this letter, we propose an interconnect network architecture designed specifically for a chiplet system targeting sparse large models. The architecture comprises a compression network built with grouped multiplexers (MUXs) and a recovery network based on a BENES network. Compared to previous works, our network achieves an area efficiency improvement of 1.13×–1.44× and a power efficiency gain of 1.34×–1.57×, while delivering an average throughput improvement of 1.6× on Llama2‐7B at a sparsity of 0.5‐0.7.