Efficient AES SubBytes Implementation for IoT Devices Using Composite Field Arithmetic and Polynomial Ring Representation

The SubBytes operation in the Advanced Encryption Standard (AES) is a critical step performed over the extended field GF(2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup>), defined using the irreducible polynomial p(x) = x<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup>+x<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup>+x<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>+x+1. However, its implementation using Look-Up Tables (LUTs) on Field Programmable Gate Arrays (FPGAs) is computationally intensive and resource-consuming. This poses a significant challenge for resource-constrained IoT devices, where efficient hardware utilization is critical. Previous studies have explored composite field arithmetic GF((2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup>)<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) to reduce complexity by mapping 8-bit elements from GF(2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup>) to GF((2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup>)<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>). Although these approaches reduce resource usage compared to traditional methods, they primarily rely on polynomial basis (PB)-based arithmetic, which still requires significant LUT resources. To address this limitation, this study proposes an advanced solution by optimizing inverse operations using polynomial ring representation (PRR) in the composite field. By decomposing 8-bit operations into 4-bit computations and leveraging PRR, the method significantly reduces LUT consumption while maintaining AES security and encryption throughput. Experimental validation on an FPGA demonstrates its feasibility for resource-constrained IoT applications, offering a practical and efficient approach to hardware-accelerated AES encryption.