Efficient Three-Operand Parallel Prefix Adder using Weinberger Architecture: Design and Applications

The Weinberger adder represents an essential advanced component in modern computing because it supports high-performance data processing requirements of digital systems. Addition of binary numbers represents a fundamental operation for these systems so we need to study algorithms together with recurrence structures while evaluating energy usage and wire trade-offs and circuit design methods at the system level. The research goal is to develop and analyze an energy-efficient VLSI adder built with Weinberger architecture to achieve maximum performance speed while reducing power usage. The parallel design of Weinberger adder includes a dual-bit selective addition block that improves both carry transfer and computation speed. The research presents a new approximation method for addition through Weinberger recursion that receives Vivado-based implementation and evaluation. Weinberger architecture demonstrates flexibility that enables CMOS implementation thus making it an appealing choice for contemporary VLSI designs. The implementation demonstrates the adjustable nature of Weinberger adders thus enabling their deployment for real-time multimedia processing in addition to AI-based imaging systems and cryptographic security applications.