Design of 8 bit Arithmetic Logic Unit for Signal Processing Applications using Verilog

This work built an 8-bit arithmetic logic unit. The arithmetic logic unit is the fundamental building block of every signal processing operation. ALU is designed for performing 16 operations including addition, subtraction, multiplication, logical, bitwise, shifting, increment and decrement. Three inputs, four select lines are given to ALU as inputs and output is obtained. This ALU is implemented in Vivado 2024 software using Verilog language and FPGA target device selected is xc7a100tcsg324-1. Two methods are used to implement ALU. ALU is implemented using behavioral and structural level modelling style. Synthesis results of both the methods are calculated.