ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process

With the advancement of modern nanoscale technology nodes, Static Timing Analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce ASAP, a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs Neural Process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.

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Publication Details

Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Published
2025-06-19
DOI
https://doi.org/10.1109/tcad.2025.3581474
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process

Wei Xing, Longze Wang, Nikolaos Sketopoulos, Yuanqing Cheng et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded Systems Design Techniques
article

ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process

Wei Xing, Longze Wang, Nikolaos Sketopoulos, Yuanqing Cheng, Zhelong Wang, Christos Sotiriou, Ning Xu
article en

Abstract

With the advancement of modern nanoscale technology nodes, Static Timing Analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce ASAP, a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs Neural Process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsVol. 45(1)
University of Thessaly (GR), Wuhan University of Technology (CN), Beihang University (CN), University of Sheffield (GB)
National Natural Science Foundation of China
Openalex Percentile: Top 87%
Embedded Systems Design Techniques
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ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process — Wei Xing, Longze Wang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025) | TGRS Research Map | TGRS