A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-Mode Range With <86 fJ · ns EDP

This paper presents a high-speed, low kickback noise dynamic comparator featuring a modified three-stage architecture that demonstrates rail-to-rail input common-mode voltage (Vi,cm) operation. The proposed design utilizes parallel NMOS and PMOS pre-amplifier signal paths, which feed into a modified Strong-Arm latch. To ensure high-speed performance across the full 0-Vdd Vi,cm range, a PMOS pre-amplifier and two-stage NMOS pre-amplifier are employed. The additional amplification stage between the NMOS pre-amplifier and the latch allows the use of NMOS input pairs in latch for NMOS pre-amplification stage as well. This architecture enhances Vi,cm range and also improves kickback noise immunity by leveraging the complementary noise contributions of the NMOS and PMOS signal paths. The proposed comparator maintains Vi,cm insensitivity and robust speed performance throughout the entire Vi,cm range. Fabricated in 180-nm CMOS technology, the prototype achieves a relative CLK-Q delay of less than 210 ps and an energy-delay product (EDP) below 86 fJ∙ ns, for 1.8 V supply.