A 17-fJ/conv-step FoM _w and 259-um ² 7-Bit C-CIDAC SAR ADC

This paper presents an energy and area efficient capacitive and charge-injection DAC SAR(C-CIDAC SAR) analog-to-digital converter(ADC) using both CDAC and CIDACs. An optimum C-CIDAC structure is analyzed, and a compact CI cell design and its simple digital control logic, such as pulse gating, are proposed. Targeting the slice ADC requirement of a timeinterleaved ADC, it occupies an area of 0.000259 mm2 in a 28-nm CMOS process and consumes a power of 0.835 mW at a sampling frequency of 700 MHz. The proposed C-CIDAC SAR ADC achieves the maximum SNDR of 38.7 dB and a FoMw of 17.03 fJ/conv-step, which is the best performance among ADCs based on the CI method.