One-step-annealing-process constructed WSe<sub>2</sub> complementary transistors

Two-dimensional (2D) semiconductor materials exhibit tremendous potential for post-Moore integrated circuits due to their unique physical properties and superior electrical characteristics. However, critical challenges in polarity modulation and complementary integration have significantly hindered the practical applications of 2D materials. The development of compatible polarity-modulation techniques has emerged as a critical step in achieving device functional integration for constructing 2D materials-based complementary circuits. This study innovatively proposes a one-step-annealing-driven polarity-modulation strategy for 2D semiconductors. It is demonstrated in this study that the conduction behavior of Pd-contacted WSe<sub>2</sub> transistors transitions from n-type to p-type dominance after annealing, while Cr-contacted devices maintain n-type dominance. Based on this polarity-modulation strategy, by selectively fabricating source and drain electrodes with different metal materials (Pd and Cr) on the same WSe<sub>2</sub>, combined with a one-step annealing process, the monolithic integration of complementary transistors is achieved, thereby realizing inverter function through device interconnection. The fabricated inverters exhibit a high voltage gain of 23 and a total noise margin of 2.3 V(0.92 <i>V</i><sub>dd</sub>) at an applied <i>V</i><sub>dd</sub> of 2.5 V. This work not only establishes a novel technical pathway for polarity modulation in 2D materials but also provides crucial technological support for developing 2D semiconductor-based complementary logic circuits.