A Comparative Study on the Parameter Degradation of SiC FETs and SiC MOSFETs under Power Cycling Tests

This paper provides a comprehensive degradation analysis of SiC FETs under accelerated power cycling tests, covering both static electrical parameters and dynamic characteristics, and compares them with SiC MOSFETs. For the static characteristics, SiC FETs exhibit significant increases in on-state resistance and junction-to-case thermal resistance after the accelerated aging tests, primarily due to packaging degradation and intrinsic solder layer delamination, respectively. In contrast, SiC MOSFETs show greater susceptibility to gate oxide deterioration and a pronounced shift in threshold voltage. Dynamic analysis, conducted via the double-pulse test after the power cycling, reveals distinct degradation patterns. For SiC FETs, the Miller plateau voltage and its duration increase slightly during the turn-on transient, while the turn-off Miller plateau duration extends substantially. Conversely, the aged SiC MOSFETs experience a modest reduction in the corresponding parameters for turn-off performance but a significant increase for turn-on performance. The findings obtained from this study indicate that on-state resistance and junction-to-case thermal resistance serve as reliable aging indicators for SiC FETs, with aging notably affecting their turn-off process, while for SiC MOSFETs, the threshold voltage stands out as a sensitive aging marker, with the dynamic turn-on performance being more prominently impacted by aging.