Design of a General-Purpose CNN Accelerator

With the widespread application of deep learning technologies, achieving efficient Convolutional Neural Network (CNN) inference on resource-constrained edge devices has become a key issue. Field-Programmable Gate Arrays (FPGA) are increasingly crucial in deploying CNN inference models. This paper proposes an FPGA-based convolutional operation accelerator that allows the host to flexibly control computation tasks through opcodes and configuration parameters. Additionally, effective optimization techniques are employed in our work. Specifically, we first transform convolution operations of arbitrary sizes into matrix multiplication forms. The user only needs to input the matrix dimensions before computation, and the accelerator will automatically handle the on-chip cache address allocation. This provides excellent flexibility and generality, making it suitable for accelerating various neural network structures. Not only do we fully utilize the fine-grained pipelining characteristics of the Matrix Processing Unit itself, but we also introduce coarse-grained pipelining during the weight padding and matrix multiplication stages. This strategy allows the Matrix Processing Unit to perform multiply-accumulate operations on the current weights while filling the next round of convolution weights, effectively hiding the memory access latency caused by weight padding. Experiments were conducted on an FPGA test platform based on the Xilinx Zynq UltraScale+ MPSoC XCZU3EG, and the proposed architecture achieved a throughput rate of 38.5 GOPS.