A 12-bit 100-MS/s Pipeline SAR ADC for Professional Medical Field

This paper presents a high-precision, low-power pipeline-SAR ADC designed for wearable device for professional medical use. The proposed ADC consists of residue amplifier, digital control circuit and two SAR ADCs. In both the first and second stage of the proposed ADC, the time sequence of monotonic capacitor switching is adopted, which reduces the power consumption of capacitor array and total capacitance. In addition, an interstage gain error shaping technique is introduced into the capacitor array of two SAR ADCs, which reduces the influence of gain error introduced by residue amplifier. Redundant bit calculation is also used, which tolerates some nonlinearity of the circuit. The ADC is simulated based on 65nm technology, achieves 61 dB SNDR under the input signal of 10MHz.

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Publication Details

Published
2025-04-18
DOI
https://doi.org/10.1109/eeice65049.2025.11034039
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.67

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article

A 12-bit 100-MS/s Pipeline SAR ADC for Professional Medical Field

Songjie Liu, Jiajun He, Shijie Feng, Demin Wang et al.
1 citations
Analog and Mixed-Signal Circuit Design
0.67
article

A 12-bit 100-MS/s Pipeline SAR ADC for Professional Medical Field

Songjie Liu, Jiajun He, Shijie Feng, Demin Wang, Jianguo Hu
article en
1 citations

Abstract

This paper presents a high-precision, low-power pipeline-SAR ADC designed for wearable device for professional medical use. The proposed ADC consists of residue amplifier, digital control circuit and two SAR ADCs. In both the first and second stage of the proposed ADC, the time sequence of monotonic capacitor switching is adopted, which reduces the power consumption of capacitor array and total capacitance. In addition, an interstage gain error shaping technique is introduced into the capacitor array of two SAR ADCs, which reduces the influence of gain error introduced by residue amplifier. Redundant bit calculation is also used, which tolerates some nonlinearity of the circuit. The ADC is simulated based on 65nm technology, achieves 61 dB SNDR under the input signal of 10MHz.

Sun Yat-sen University (CN), South China Normal University (CN)
National Science and Technology Major Project
Openalex Percentile: Top 30%
Analog and Mixed-Signal Circuit Design
0.67
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A 12-bit 100-MS/s Pipeline SAR ADC for Professional Medical Field — Songjie Liu, Jiajun He, et al. · (2025) | TGRS Research Map | TGRS