Multi-channel High-Speed ADC Acquisition System Based on JESD204B Protocol

With the application of the converter-specific interface protocol JESD204B, the bandwidth, dynamics, and channel synchronization performance of ADC converters have been enhanced to a new high level. In this paper, we design a general-purpose multi-channel high-speed ADC acquisition system based on JESD204B protocol, and develop the JESD204B interface IP with independent intellectual property rights on the FPGA hardware platform, and the key device is the JESD204B interface IP. JESD204B interface IP is developed on the FPGA hardware platform, and the key devices are TI's latest ADC12J1600 converter and the FPGA which embedded high speed transceivers. In the paper, the system composition, the principle of multi-device synchronization, JESD204B protocol IP development are elaborated in detail, and the ENOB indexes of this acquisition system are tested and analyzed to verify the correctness of the design. The system adopts a generalized design, and the ENOB index of this system is analyzed to verify the correctness of the design. This system adopts generalized design, flexible structure and function expansion, and can be used in the prototype prototype of various fields that have the demand for Gigahertz high-speed sampling. The system can be used in prototypes in various fields that require high speed sampling in GHz.