Implementation Architecture of Enhanced Haze Removal Method for Advanced Driving Assistance System

The Advanced Driver Assistance System (ADAS) relies on a clear view of the road and traffic. Images get hazy due to atmospheric variables; hence, an effective method for dehazing images is sought and desired for use with ADAS gear. The study presents the results of an effective method for image dehazing and the accompanying hardware architecture. To eliminate the haze depending on the dark channel previously, the Approximate Transmission Map Estimation (TME) and the Atmospheric Light Estimation (ALE) are utilized. Along with line buffers and register arrays, the optimized hardware components are designed. For the Zynq FPGA board, the whole design is simulated and synthesized in Verilog HDL. We compare the suggested technique to previous works and find that it has good performance measures including SSIM, MSE, and PSNR. Data is analyzed in terms of FPGA hardware to determine hardware utilization.

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Publication Details

Published
2025-04-25
DOI
https://doi.org/10.1109/icdcece65353.2025.11035502
Primary Topic
Image Enhancement Techniques
Type
article
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article

Implementation Architecture of Enhanced Haze Removal Method for Advanced Driving Assistance System

Sireesha Pendem, Harish Babu Gade, Venkata Krishna Odugu, S. Srikanth
Image Enhancement Techniques
article

Implementation Architecture of Enhanced Haze Removal Method for Advanced Driving Assistance System

Sireesha Pendem, Harish Babu Gade, Venkata Krishna Odugu, S. Srikanth
article en

Abstract

The Advanced Driver Assistance System (ADAS) relies on a clear view of the road and traffic. Images get hazy due to atmospheric variables; hence, an effective method for dehazing images is sought and desired for use with ADAS gear. The study presents the results of an effective method for image dehazing and the accompanying hardware architecture. To eliminate the haze depending on the dark channel previously, the Approximate Transmission Map Estimation (TME) and the Atmospheric Light Estimation (ALE) are utilized. Along with line buffers and register arrays, the optimized hardware components are designed. For the Zynq FPGA board, the whole design is simulated and synthesized in Verilog HDL. We compare the suggested technique to previous works and find that it has good performance measures including SSIM, MSE, and PSNR. Data is analyzed in terms of FPGA hardware to determine hardware utilization.

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Image Enhancement Techniques
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