A Dual-bit Redundant MDAC Design for Pipeline ADC

MDAC plays an important role in pipeline ADC, this paper analyzes the non-ideal factors of MDAC and designs an MDAC that can eliminate these non-ideal factors. The MDAC is designed with 2 significant bits, 2 correction bits, and an inter-stage gain of 4. The MDAC increases the inter-stage correction interval through the dual-bit shifting correction method, reduces the input range of the post-stage, and the effect of comparator offset error on the results is suppressed. At the same time, by the op amp design and the capacitor trimming controlled by the fuse trimming array, which reduces the gain error between stages. The simulation results show that the MDAC’s SNR is 92.54dB, the SFDR is 95.59dB, the THD is -95.02dB, and the ENOB is 15.08bit when the sampling rate is 125Msps and the input signal frequency is 11.59 MHz, indicating that the MDAC has good performance.