DC-18GHz, SFDR 72.94dB Sampling-Hold Amplifier in 0.18-μm SiGe process

This study presents a novel ultra-wideband sampling-hold amplifier (SHA) based on a full differential architecture, targeting a sampling rate of 4GSPS and a bandwidth exceeding 18GHz. Implemented using 0.18μm SiGe BiCMOS technology, this circuit innovatively incorporates a switch emitter follower (SEF) as its core structure, featuring separate control mechanisms for the base and collector of the SEF to mitigate parasitic capacitance effects while reducing device size. Furthermore, a cross-coupled feedback network is introduced to eliminate feedthrough noise, significantly enhancing signal linearity in hold mode. Simulation results demonstrate that the circuit achieves a bandwidth of 20.2GHz in hold state; at an input frequency of 4GHz, the peak spurious-free dynamic range (SFDR) reaches 72.94 dB. This design approach reconciles the competing demands for ultra-wide bandwidth and high linearity, holding significant potential for applications in high-speed data acquisition systems.